Hello i am writing code for spi slave module and i want to use only SCK provided by master block. I mean dont want to use system clock in Slave. So when write sequential logics can i write
always@(posedge SCK)
is it right as this is a slower (serial) clock povided by masters.

On 10/11/2023 06:47 AM, khan wrote:
> Hello i am writing code for spi slave module and i want to use only SCK provided by master block. I mean dont want to use system clock in Slave. So when write sequential logics can i write
> always@(posedge SCK)
> is it right as this is a slower (serial) clock povided by masters.

I wrote a spi slave in VHDL clocked by SCK. You have to pay attention to several issues:

1. Yes for best performance you clock your SPI slave with the incoming SCK. But since the SCK is in general asynchronous with respect to your system clock, the signals communicating to your system must be synchronized with several stages. You must have TX & RX FIFOs, and the TX-read & RX-write signals must be synced to the system clock and trimmed to one clock cycle.

2. For simplicity, support just one SPI mode, say Mode 0 (CPHA=0 & CPOL=0). In that mode, the SPI slave engine clocks on the rising edge of SCK; you strobe in the incoming MOSI on the rising edge. You have to correct the outgoing MISO with a latch so it changes values on the falling edge of SCK per the SPI spec.

3. You asynchronously reset your bit counter using the de-assertion of SPISEL. That part's no problem. What may be an issue is: you must asynchronously load your shifter, else your first word will not be issued correctly. Your synthesizer may not support asynchronous loads.